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ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 25 features ? 168 pin jedec standard, 8 byte dual in-line memory module ? 8mx72 dual bank fast page mode dimm ? performance: ? all inputs and outputs are lvttl (3.3v) or ttl (5.0v) compatible ? single 3.3v 0.3v or 5.0v 0.5v power supply ? au contacts ? optimized for ecc applications ? system performance bene?ts: -buffered inputs (except ras, data) -reduced noise (32 v ss /v cc pins) -4 byte interleave enabled -buffered pds ? fast page mode, read-modify-write cycles ? refresh modes: ras-only, cbr and hidden refresh ? 4096 refresh cycles distributed across 64ms ? 12/10 addressing (row/column) ? card size: 5.25" x 1.5" x 0.354" ? dram s in soj package description ibm11m8730c is an industry standard 168-pin 8-byte dual in-line memory module (dimm) which is organized as an 8mx72 high speed memory array, designed for ecc applications, and is configured as 2 4mx72 banks. the dimm uses 36 4mx4 drams in soj packages. improved system performance is provided by the on-dimm buffering of selected input signals. the specified timings include all buffer, net and skew delays, which simplifies the memory subsystem design analysis. the data and ras signals are not buffered, which preserves the dram access specifi- cations of 60ns and 70ns. presence detect (pd) and identification detect (id) bits provide information about the dimm density, addressing, performance and features. pd bits can be dotted at the system level and activated for each dimm position using the pd enable ( pde) signal. id bits also allow detection of card features, and may be dot-ord at the system level to provide information for the entire dimm bank. for example, the system will determine that ecc dimms are installed if pd8 is low (0). id0 need not be sensed since both x72 and x80 ecc dimms will function in a x72 bank. all ibm 168-pin dimms provide a high performance, flexible 8-byte interface in a 5.25 long space-saving footprint. related products are the x64 and x72 par- ity (5v) dimms and ecc dimms (5v and 3.3v). -60 -70 t rac ras access time 60ns 70ns t cac cas access time 20ns 25ns t aa access time from address 35ns 40ns t rc cycle time 110ns 130ns t pc fast page mode cycle time 40ns 45ns card outline (3.3v) 1 85 10 94 11 95 40 124 41 125 84 168 (front) (back) see detail a detail a for 5.0v version ibm11m1730bb1m x 72 e10/10, 3.3v, au. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 25 50h8039 sa14-4629-02 released 6/96 pin description ras0, ras1, ras2, ras3 row address strobe v cc power (3.3v or 5.0v) cas0, cas1, cas4, cas5 column address strobe (buffered) v ss ground we0, we2 read/write input (buffered) nc no connect oe0, oe2 output enable (buffered) pd1 - pd8 presence detects (buffered) a0, b0, a1 - a11 address inputs (buffered) pde presence detect enable dqx data input/output id0 - id1 id bits pinout pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side 1 v ss 85 v ss 22 dq17 106 dq53 43 v ss 127 v ss 64 nc 148 nc 2 dq0 86 dq36 23 v ss 107 v ss 44 oe2 128 nc 65 dq25 149 dq61 3 dq1 87 dq37 24 nc 108 nc 45 ras2 129 ras3 66 dq26 150 dq62 4 dq2 88 dq38 25 nc 109 nc 46 cas4 130 cas5 67 dq27 151 dq63 5 dq3 89 dq39 26 v cc 110 v cc 47 nc 131 nc 68 v ss 152 v ss 6 v cc 90 v cc 27 we0 111 nc 48 we2 132 pde 69 dq28 153 dq64 7 dq4 91 dq40 28 cas0 112 cas1 49 v cc 133 v cc 70 dq29 154 dq65 8 dq5 92 dq41 29 nc 113 nc 50 nc 134 nc 71 dq30 155 dq66 9 dq6 93 dq42 30 ras0 114 ras1 51 nc 135 nc 72 dq31 156 dq67 10 dq7 94 dq43 31 oe0 115 nc 52 dq18 136 dq54 73 v cc 157 v cc 11 dq8 95 dq44 32 v ss 116 v ss 53 dq19 137 dq55 74 dq32 158 dq68 12 v ss 96 v ss 33 a0 117 a1 54 v ss 138 v ss 75 dq33 159 dq69 13 dq9 97 dq45 34 a2 118 a3 55 dq20 139 dq56 76 dq34 160 dq70 14 dq10 98 dq46 35 a4 119 a5 56 dq21 140 dq57 77 dq35 161 dq71 15 dq11 99 dq47 36 a6 120 a7 57 dq22 141 dq58 78 v ss 162 v ss 16 dq12 100 dq48 37 a8 121 a9 58 dq23 142 dq59 79 pd1 163 pd2 17 dq13 101 dq49 38 a10 122 a11 59 v cc 143 v cc 80 pd3 164 pd4 18 v cc 102 v cc 39 nc 123 nc 60 dq24 144 dq60 81 pd5 165 pd6 19 dq14 103 dq50 40 v cc 124 v cc 61 nc 145 nc 82 pd7 166 pd8 20 dq15 104 dq51 41 nc 125 nc 62 nc 146 nc 83 id0 167 id1 21 dq16 105 dq52 42 nc 126 b0 63 nc 147 nc 84 v cc 168 v cc note: all pin assignments are consistent for all 8 byte versions. ordering information part number organization speed addr. leads dimension power notes ibm11m8730c-60 8mx72 60ns 12/10 au 5.25x1.5x 0.354 5.0v ibm11m8730c-70 70ns ibm11m8730c-60j 60ns 1 ibm11m8730c-70j 70ns 1 IBM11M8730CB-60 60ns 3.3v IBM11M8730CB-70 70ns IBM11M8730CB-60j 60ns 1 IBM11M8730CB-70j 70ns 1 1. dram package designator appended to speed portion of part number on assemblies beginning with dram die rev e. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 25 block diagram dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d0 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 we0 ras0 oe0 d1 d2 d3 d4 d5 d7 dq24 dq25 dq26 dq27 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d6 cas0 dq32 dq33 dq34 dq35 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d8 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d23 d25 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d24 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d26 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d18 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d19 d20 d21 d22 ras1 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d9 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 we2 ras2 oe2 d10 d11 d12 d13 cas4 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d27 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d28 d29 d30 d31 dq56 dq57 dq58 dq59 dq64 dq65 dq66 dq67 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d14 d16 dq60 dq61 dq62 dq63 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d15 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d32 d34 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d33 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d35 dq68 dq69 dq70 dq71 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d17 ras3 v cc v ss d0 - d35, buffers d0 - d35, buffers a0 a0: drams d0 - d8, d18 - d26 b0 a0: drams d9 - d17, d27 - d35 a1-an a1-an: drams d0 - d4, d9 - d12, d18 - d22, d27 - d30 a1-an: drams d5 - d8, d13 - d17, d23 - 26, d31 - 35 v ss pde pd1 - 8 (when=0, 1=nc) cas5 cas1 discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 25 50h8039 sa14-4629-02 released 6/96 truth table function ras cas we oe row address column address pde dqx standby h h ? x xxxxx high impedance read l l h l row col x valid data out early-write l l l x row col x valid data in late-write / rmw l l h ? ll ? h row col x valid data out, valid data in fast page mode - read 1st cycle l h ? l h l row col x valid data out subsequent cycles l h ? l h l n/a col x valid data out fast page mode - write 1st cycle l h ? l l x row col x valid data in subsequent cycles l h ? l l x n/a col x valid data in fast page mode - rmw 1st cycle l h ? lh ? ll ? h row col x valid data out, valid data in subsequent cycles l h ? lh ? ll ? h n/a col x valid data out, valid data in ras-only refresh l h x x row n/a x high impedance cas-before- ras refresh h ? l lhxxxx high impedance hidden refresh read l ? h ? l l h l row col x data out write l ? h ? l l h x row col x data in read presence detects xxxxxxl not affected (pd bits valid) presence detect pin -60 -70 pd1 (pd1 - pd4: addressing/density) 0 0 pd2 00 pd3 11 pd4 11 pd5 (edo detection) 00 pd6 (pd6 - pd7: speed) 10 pd7 11 pd8 (parity/ecc designator) 0 0 id0 (dimm type/width) 00 id1 (refresh mode) 00 1. pd1-8 are buffered outputs (0 = driven to v ol , 1 = open) 2. id0-1 are unbuffered outputs (0 = v ss , 1 = open) 3. pde should be tied high or low at system level if not used discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 25 absolute maximum ratings symbol parameter rating (3.3v) rating (5.0v) units notes v cc power supply voltage -0.5 to +4.6 -1.0 to +7.0 v 1 v in input voltage -0.5 to min (v cc + 0.5, 4.6) -0.5 to min (v cc + 0.5, 7.0) v1 v out output voltage -0.5 to min (v cc + 0.5, 4.6) -0.5 to min (v cc + 0.5, 7.0) v1 t opr operating temperature 0 to +70 0 to +70 c 1 t stg storage temperature -55 to +125 -55 to +125 c 1 p d power dissipation 9.7 14.8 w 1, 2 i out short circuit output current 50 50 ma 1 i outpd short circuit output current (pd) 60 60 ma 1 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated is not implied. exposure to absolute maximum rating con- dition for extended periods may affect reliability. 2. maximum power occurs when all banks are active (refresh cycle). recommended dc operating conditions (t a = 0 to 70 c) symbol parameter 3.3v 5.0v units notes min typ max min typ max v cc supply voltage 3.0 3.3 3.6 4.5 5.0 5.5 v 1 v ih input high voltage 2.0 v cc + 0.5 2.4 v cc + 0.5 v 1, 2 v il input low voltage -0.5 0.8 -0.5 0.8 v 1, 2 1. all voltages referenced to v ss. 2. v ih may overshoot to v cc + 1.2v for pulse widths of 4.0ns with 3.3 volt, or v cc + 2.0v for pulse widths of 4.0ns (or v cc + 1.0v for 8.0ns) with 5.0 volt. additionally, v il may undershoot to -2.0v for pulse widths 4.0ns (or -1.0v for 8.0ns). pulse widths measured at 50% points with amplitude measured peak to dc reference. capacitance (t a = 0 to +70 c, v cc = 3.3v 0.3v or 5.0v 0.5v) symbol parameter max units c i1 input capacitance a0, b0 13 pf a1 - a11 18 c i2 input capacitance ( ras) 80 pf c i3 input capacitance ( cas, we, oe) 18 pf c i4 input capacitance ( pde) 18 pf c io1 input/output capacitance (dq x )22pf c o1 output capacitance (pd) 15 pf c o2 output capacitance (id) 5pf discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 25 50h8039 sa14-4629-02 released 6/96 dc electrical characteristics (t a = 0 to +70?c, v cc = 3.3v 0.3v or v cc = 5.0v 0.5v) symbol parameter min. max. units notes i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min.) -60 1386 ma 1, 2, 3 -70 1206 i cc2 standby current (ttl) power supply standby current ( ras = cas = v ih ) 72 ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas = v ih : t rc = t rc min) -60 1386 ma 1, 3, 4 -70 1206 i cc4 fast page mode current average power supply current, fast page mode ( ras = v il , cas, address cycling: t pc = t pc min) -60 1206 ma 1, 2, 3 -70 1026 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) 36 ma i cc6 cas before ras refresh current average power supply current, cas before ras mode ( ras, cas, cycling: t rc = t rc min) -60 1386 ma 1, 3, 4 -70 1206 i i(l) input leakage current input leakage current, any input (0.0 v in (v cc + 0.3v)), all other pins not under test = 0v cas, we, oe, a0, b0 -10 +10 m a a1 - a11, dq -20 +20 ras -90 +90 i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -20 +20 m a v oh output level (ttl) output h level voltage (i out = -2.5ma for 3.3v, or i out = -5ma for 5.0v) 2.4 v cc v v ol output level (ttl) output l level voltage (i out = +2.1ma for 3.3v, or i out = +4.2ma for 5.0v) 0.0 0.4 v 1. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 2. i cc1 and i cc4 depend on output loading. speci?ed values are obtained with the output open. 3. address can be changed once or less while ras =v il . in the case of i cc4 , it can be changed once or less when cas =v ih . 4. refresh current is speci?ed for 1 bank active and 1 bank standby. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 25 ac characteristics (t a = 0 to +70 c, v cc = 3.3v 0.3v or 5.0v 0.5v) 1. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 2. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required. 3. the speci?ed timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the dram device timings. the data and ras signals are not buffered, which preserves the drams access speci?cations of 60ns and 70ns. 4. ac measurements assume t t = 5ns. . read, write, read-modify-write and refresh cycles (common parameters) symbol parameter -60 -70 unit notes min max min max t rc random read or write cycle time 110 130 ns t rp ras precharge time 40 50 ns t cp cas precharge time 10 10 ns t ras ras pulse width 60 10k 70 10k ns t cas cas pulse width 15 10k 20 10k ns 1 t asr row address setup time 5 5 ns t rah row address hold time 8 8 ns t asc column address setup time 2 2 ns t cah column address hold time 10 10 ns t rcd ras to cas delay time 18 40 18 45 ns 2 t rad ras to column address delay time 13 25 13 30 ns 3 t rsh ras hold time 20 25 ns t csh cas hold time 58 68 ns t crp cas to ras precharge time 10 10 ns t odd oe to d in delay time 20 25 ns 4 t dzo oe delay time from d in -2-2ns 5 t dzc cas delay time from d in -2-2ns 5 t ar column address hold time referenced to ras 6 t t transition time (rise and fall) 3 30 3 30 ns 1. the minimum t cas requires t csh to be met for both writes and reads. also, because of the buffer, the minimum t cas for a read cycle must be extended to guarantee the data out window (t oh ) in the application. for example, a t cas of 15ns plus a minimum t oh of 2ns would result in turning data out of the dimm at 17ns (3ns before max t cac of 20ns). 2. operation within the t rcd (max) limit ensures that t rac (max) can be met. the t rcd (max) is speci?ed as a reference point only: if t rcd is greater than the speci?ed t rcd (max) limit, then access time is controlled by t cac. 3. operation within the t rad (max) limit ensures that t rac (max) can be met. the t rad (max) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa. 4. either t cdd or t odd must be satis?ed. 5. either t dzc or t dzo must be satis?ed. 6. this timing parameter is not applicable to this product, but applies to a related product in this family. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 25 50h8039 sa14-4629-02 released 6/96 write cycle symbol parameter -60 -70 unit notes min max min max t wcs write command set up time 2 2 ns 1 t wch write command hold time 17 17 ns t wp write command pulse width 15 15 ns t rwl write command to ras lead time 20 25 ns t cwl write command to cas lead time 17 22 ns t wcr write command hold time referenced to ras ns 2 t dhr data hold time referenced to ras ns 2 t ds d in setup time -2 -2 ns 3 t dh d in hold time 17 20 ns 3 1. t wcs , t rwd , t cwd , t awd , and t cpw are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.), t awd 3 t awd (min.) and t cpw 3 t cpw (min.)(fast page mode), the cycle is a read-modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. 2. this timing parameter is not applicable to this product, but applies to a related product in this family. 3. data-in set-up and hold is measured from the latter of the two timings, cas or we. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 25 read cycle symbol parameter -60 -70 unit notes min max min max t rac access time from ras 6070ns 1, 2 t cac access time from cas 2025ns 1, 2 t aa access time from address 35 40 ns 1, 2 t oea access time from oe 2025ns 1, 2 t rcs read command setup time 2 2 ns t rch read command hold time to cas 2 2 ns 3 t rrh read command hold time to ras 0 0 ns 3 t ral column address to ras lead time 35 40 ns t cal column address to cas lead time 35 40 ns t clz cas to output in low-z 2 2 ns t roh ras hold to output enable ns 4 t oh output data hold time 2 2 ns t oho output data hold time from oe 22ns t oez output buffer turn-off delay from oe 2 20 2 20 ns 5 t cdd cas to d in delay time 20 20 ns 6 t off output buffer turn-off delay 2 20 2 20 ns 1. measured with the speci?ed current load and 100pf. 2. access time is determined by the latter of t rac , t cac , t cpa , t aa, t oea . 3. either t rch or t rrh must be satis?ed. 4. this timing parameter is not applicable to this product, but applies to a related product in this family. 5. t off (max) and t oez (max) de?ne the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. either t cdd or t odd must be satis?ed. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 25 50h8039 sa14-4629-02 released 6/96 fast page mode cycle symbol parameter -60 -70 unit notes min max min max t pc fast page mode cycle time 40 45 ns t rasp fast page mode ras pulse width 60 100k 70 100k ns t cprh ras hold time from cas precharge 40 45 ns t cpa access time from cas precharge 40 45 ns 1, 2 1. measured with the specified current load and 100pf. 2. access time is determined by the latter of t rac , t cac , t cpa , t aa, t oea . read-modify-write cycle symbol parameter -60 -70 unit notes min max min max t rwc read-modify-write cycle time 158 188 ns t rwd ras to we delay time 83 98 ns 1 t cwd cas to we delay time 45 55 ns 1 t awd column address to we delay time 58 68 ns 1 t oeh oe command hold time 15 15 ns 1. t wcs , t rwd , t cwd , t awd , and t cpw are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.), t awd 3 t awd (min.) and t cpw 3 t cpw (min.)(fast page mode), the cycle is a read-modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. fast page mode read-modify-write cycle symbol parameter -60 -70 unit notes min max min max t prwc fast page mode read-modify-write cycle time 83 98 ns t cpw we delay time from cas precharge 63 73 ns 1 1. t wcs , t rwd , t cwd , t awd , and t cpw are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.), t awd 3 t awd (min.) and t cpw 3 t cpw (min.)(fast page mode), the cycle is a read- modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the con- dition of the data (at access time) is indeterminate. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 25 refresh cycle symbol parameter -60 -70 unit notes min max min max t chr cas hold time ( cas before ras refresh cycle) 88ns t csr cas setup time ( cas before ras refresh cycle) 1414ns t wrp we setup time ( cas before ras refresh cycle) 1515ns t wrh we hold time ( cas before ras refresh cycle) 88ns t rpc ras precharge to cas hold time 3 3 ns t ref refresh period 64 64 ms 1 1. 4096 refreshes are required every 64ms. presence detect read cycle symbol parameter -60 -70 unit notes min max min max t pd pde to valid presence detect data 10 10 ns 1 t pdoff pde inactive to presence detects inactive 0 10 0 10 ns 2 1. measured with the specified current load and 100pf. 2. t pdoff (max) de?nes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 25 50h8039 sa14-4629-02 released 6/96 read cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t rsh t csh t crp t rah t asc t cah t asr t rad t ral t rcs t aa t oea t dzc t dzo t cdd t off t clz t cac t rac hi-z hi-z hi-z t rch t rrh : h or l t rcd t cal t oh t oho t oez t odd cas t roh t ar discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 25 write cycle (early write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rc t rcd t rsh t csh t crp t rah t asc t cah t asr t rad t wcs hi-z : h or l valid data in t wp t wch t ds t dh cas t cas t ar t wcr t dhr discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 25 50h8039 sa14-4629-02 released 6/96 write cycle (late write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rc t rsh t csh t crp t rah t asc t cah t asr t rad t rwl : h or l t wp t cwl valid data in hi-z* hi-z t dzc t oeh t oez t clz t oea t ds t odd t rcd t dh t rcs * output remains hi-z because we is latched internally following t wp min. t dzo hi-z cas t cas t ar t wcr t dhr discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 25 read-modify-write-cycle d in t oeh v ol v oh v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih t rcd t rwc t ras t csh t rsh t rp t crp t rad t rah t asc t asr t cah t cwd t awd t rwd t aa t rcs t oea t rwl t cwl t wp t dh t ds t dzc t dzo t cac t clz t odd t oez t rac address oe d in d out hi-z hi-z d out column : h or l t oho ras we hi-z * t cas * output remains hi-z because we is latched internally following twp min. cas t ar t wcr t dhr row discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 25 50h8039 sa14-4629-02 released 6/96 fast page mode read cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in t rasp t rp : h or l row column 1 column 2 column n d out 1d out 2d out n t asr t asc t rah t cah t csh t asc t cah t asc t cah t ral t rsh t pc t cp t crp t rad t rch t rcs t rch t rcs t rch t rrh t aa t rcs t aa t oea t oea t cpa t aa t oea t cpa t rac t clz t off t off t off t oez t oez t oez t dzc t dzo t cac t odd t dzo t dzc t odd t dzo t dzc t odd t cdd t clz t clz t cac t cac t rcd t cp t cal t oh t oho t oh t oho t oh t oho t cprh cas t cas t cas t cas t ar t roh discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 25 fast page mode write cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in t rasp t rp : h or l row column 1 column 2 column n t asr t asc t rah t cah t csh t asc t cah t asc t cah t rsh t rcd t pc t cp t crp t rad d in 1 d in 2 d in n t ds t dh t ds t dh t ds t dh t wp t wp t wp t wcs t wch t wcs t wch t wcs t wch t cwl t rwl t cwl t cwl t cp cas t cas t cas t cas t ar t wcr t dhr discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 25 50h8039 sa14-4629-02 released 6/96 fast page mode read-modify-write cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in t rasp t rp row column 1 column 2 column n d out 1 t asr t asc t rah t cah t csh t asc t cah t asc t cah t rsh t prwc t cp t crp t rad t aa t rcs t cpa t aa t cpa t rac t clz t dzc t dzo t cac t clz t clz t rcd t cp d out 2 d out n t cac t cac d in 1 t odd d in 2 t odd d in n t odd t ds t ds t ds t dh t dh t dh t wp t wp t wp t rcs t rcs t cwd t cpw t cwd t awd t rwd t aa t cwl t cwl t cwl t rwl t cpw t awd t cwd t awd t oez t oho t oez t oho t oez t oho t oea t oea t oea t oeh t oeh t oeh cas t cas t cas t cas : h or l t ar t wcr t dhr discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 25 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z : h or l note: we, oe, d in are h or l t rpc t crp cas discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 25 50h8039 sa14-4629-02 released 6/96 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v oh v ol t ras t rp oe v ih v il d out v oh v ol hi-z : h or l t off t oez hi-z t odd t chr rc t t wrh t wrp t note: address is h or l rpc t cp t cdd t rpc t csr t wrh t wrp t csr cas discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 25 hidden refresh cycle (read) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t ras t rp t rc t crp t rah t asc t cah t asr t rad t rcs t dzc t odd t oez t cdd t clz t cac t rac hi-z hi-z hi-z : h or l t rp t chr rsh t rcd t t rrh t wrp t wrh t rc t dzo t ral t off cas t oea t ord t aa discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 25 50h8039 sa14-4629-02 released 6/96 hidden refresh cycle (write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data t ras t ras t rp t rc t crp t rah t asc t cah t asr hi-z : h or l t rp t chr rsh t t ds t dh t wch wcs t t wrp t wrh t rc t wp t rcd cas discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 25 presence detect read cycle pde v ih v il pd1-pd8 v oh v ol valid presence detect t pdoff * *pd pins must be pulled high at next level of assembly t pd discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 25 50h8039 sa14-4629-02 released 6/96 layout drawing 3.3v/5.0v r 1.00 .0393 note: all dimensions are typical unless otherwise stated. 2.0 .078 3.0 .118 detail a scale: 4/1 millimeters inches r 1.00 .0393 2.0 .078 3.0 .118 detail b 3.3v version 5.0v version 66.68 (3.3v), 65.68 (5.0v) 2.63 (3.3v), 2.586 (5.0v) 6.35 .250 43.18 (3.3v), 42.18 (5.0v) 1.70 (3.3v), 1.661(5.0v) 1.27 pitch .050 1.00 width .039 see detail a/b 1.50 38.1 (2) 0 3.1877 .1255 133.35 5.25 131.35 5.171 127.35 5.014 .118 3.0 (2x) 4.00 .157 .700 17.78 front 9.00 .354 max. side 1.27 0.10 .050 .004 + _ + _ 2.702 .130 min. discontinued (9/98 - last order; 3/99 - last ship)
ibm11m8730c IBM11M8730CB 8m x 72 dram module 50h8039 sa14-4629-02 released 6/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 25 revision log rev contents of modi?cation 1/96 initial release. 3/96 improved power dissipation improved dc electrical characteristics: i cc1, i cc3, i cc4, i cc6 updated address capacitances added timing: t cas improved timings: t cah, t crp, t dh, t rrh, t oez, t cdd, t off, t oeh the cbr timing diagram was changed to allow cas to remain low for back-to-back cbr cycles. hidden refresh cycle (read) timing diagram was changed to show data being turned off with cas not ras 5/96 updated ordering information discontinued (9/98 - last order; 3/99 - last ship)
intern ational business machines corp.1996 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. sa14-4634-03 a discontinued (9/98 - last order; 3/99 - last ship)

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